A U F G A B E d e r Abschlussarbeit im Master-Studiengang Embedded Systems Engineering

A U F G A B E d e r Abschlussarbeit
im Master-Studiengang
Embedded Systems Engineering (ISE)
für:Aida Sinanovic, 3056314
gestellt von:Prof. Dr.-Ing. Axel Hunger
Thema: Development of a Clock Tree Visualizer as Design Aid for Time sensitive Integrated Circuits
Nowadays, in modern Systems on Chip there are huge clock trees because of their complexity. The design of the clock network in an SoC becomes more complex for a number of reasons and among them: customer  requirements to serve their application needs, test requirements (scan-stuck-at, scan-delay, iddq) and analogue characterization and analysis requirements.  The clock tree structure distributes clock signals within a system. It is possible to have multiple clock sources connected to the clock tree. The sinks of the clock tree are all flip-flops and memories of a SoC. Beside flip-flops in the clock tree, we have clock gating cells, which allow power saving and multiplexers which enable alternative clock paths in the tree (switching clock sources) .Because of this complexity and  a poor support of existing EDA tools, it has become very difficult for the development teams to control the clock tree implementation to ensure best quality of results.

A Clock Tree Visualizer should  generate a graphical user interface (“GUI”) from a text-based netlist of a clock tree that allows an integrated circuit (“IC”) designer to visualize the clock tree in the form of symbolic gates connected in accordance with the IC design and displayed in an untangled manner.  The display may be interlaced with all the necessary design details. As a result, user could spot problematic gates relatively easily because of the more focused visualization of the clock tree.
Special emphasis of the thesis will be to develop algorithms which aim is to extract the data from clock structures, analyze them and finally visualize them to the user.

Topics are:
Show-up re-convergent clock tree elements
Common point detection of early hooked up flip-flops
Detect clock signal phase shift
Detect differences in two given clock structures – data sets.

Automatic clock tree contrains generation (timing and structural implementation)
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Aufgabensteller/Betreuer
Zweitgutachter der Abschlussarbeit: Prof. Kochs

E R K L Ä R U N G
Hiermit erkläre ich, dass ich die Arbeit bis auf die offizielle Betreuung durch den Aufgabensteller selbständig und ohne fremde Hilfe verfasst habe.

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Duisburg, den ………………. …………………………………….

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